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248
2593O–AVR–02/12
ATmega644
21.9
Register Description
21.9.1
ADMUX – ADC Multiplexer Selection Register
Bit 7:6 – REFS1:0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in
Table 21-3. If these bits are
changed during a conversion, the change will not go in effect until this conversion is complete
(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external
reference voltage is being applied to the AREF pin.
Note:
If 10x og 200x gain is selected, only 2.56V should be used as Internal Voltage Reference.
Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
These bits also select the gain for the differential channels. See
Table 21-4 for details. If these
bits are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set).
Bit
76543210
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
ADMUX
Read/Write
R/W
Initial Value
00000000
Table 21-3.
Voltage Reference Selections for ADC
REFS1
REFS0
Voltage Reference Selection
0
AREF, Internal Vref turned off
0
1
AVCC with external capacitor at AREF pin
1
0
Internal 1.1V Voltage Reference with external capacitor at AREF pin
1
Internal 2.56V Voltage Reference with external capacitor at AREF pin
Table 21-4.
Input Channel and Gain Selections
MUX4..0
Single Ended
Input
Positive Differential
Input
Negative Differential
Input
Gain
00000
ADC0
00001
ADC1
00010
ADC2
00011
ADC3
N/A
00100
ADC4
00101
ADC5