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參數(shù)資料
| 型號： | MT48LC8M16A2FB-8EIT |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 14/59頁 |
| 文件大?。?/td> | 1822K |
| 代理商： | MT48LC8M16A2FB-8EIT |
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14
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65
–
Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
SDRAM
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This
command is nonpersistent, so it must be issued each
time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH
command. The AUTO REFRESH command should not
be issued until the minimum
t
RP has been met after the
PRECHARGE command as shown in the operation sec-
tion.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 128Mb SDRAM
requires 4,096 AUTO REFRESH cycles every 64ms (
t
REF),
regardless of width option. Providing a distributed AUTO
REFRESH command every 15.625μs will meet the refresh
requirement and ensure that each row is refreshed. Alter-
natively, 4,096 AUTO REFRESH commands can be issued
in a burst at the minimum cycle rate (
t
RFC), once every
64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the SDRAM
retains data without external clocking. The SELF RE-
FRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). Once the SELF
REFRESH command is registered, all the inputs to the
SDRAM become “Don’t Care” with the exception of CKE,
which must remain LOW.
Once self refresh mode is engaged, the SDRAM pro-
vides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to
t
RAS
and may remain in self refresh mode for an indefinite
period beyond that.
The procedure for exiting self refresh requires a se-
quence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing con-
straints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
t
XSR because time is required for the completion of any
internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued every 15.625μs or less as both
SELF REFRESH and AUTO REFRESH utilize the row re-
fresh counter.
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PDF描述 |
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| MT48LC8M16A2FB-8EL | SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-8ELIT | SYNCHRONOUS DRAM |
| MT48LC8M16A2FC-75 | SYNCHRONOUS DRAM |
| MT48LC8M16A2FC-75IT | SYNCHRONOUS DRAM |
| MT48LC8M16A2FC-75L | SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC8M16A2FB-8EL | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-8ELIT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC8M16A2FC-75 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC8M16A2FC-75IT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC8M16A2FC-75L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
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