
21
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 
–
 Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
 2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
Figure 10
Random READ Accesses
CK
CK#
COMMAND
READ
READ
READ
NOP
NOP
ADDRESS
Bank,
Col 
n
Bank,
Col 
x
CL = 2
Bank,
Col 
b
Bank,
Col 
x
CL = 2.5
Bank,
Col 
b
READ
Bank,
Col
 g
COMMAND
ADDRESS
CK
CK#
DQ
DQS
DQ
DQS
DO
n
DO
x'
DO
g
DO
n'
DO
b
DO
x
DO
b'
DO
n
DO
x'
DO
n'
DO
b
DO
x
DO
b'
T0
T1
T2
T3
T2n
T3n
T4
T5
T4n
T5n
NOTE
: 1. DO 
n
 (or 
x
 or 
b
 or 
g
) = data-out from column 
n
 (or column x or column 
b 
or column 
g
).
            2. Burst length = 2 or 4 or 8 (if 4 or 8, the following burst interrupts the previous).
            3.
 n
' or 
x
' or 
b
' or 
g
' indicates the next data-out following DO 
n
 or DO 
x
 or DO 
b
 or DO 
g
, respectively
.
            4. READs are to an active row in any bank
.
            5. Shown with nominal 
t
AC, 
t
DQSCK, and 
t
DQSQ.
READ
READ
READ
NOP
NOP
Bank,
Col 
n
READ
Bank,
Col
 g
T0
T1
T2
T3
T2n
T3n
T4
T5
T4n
T5n
DON
’
T CARE
TRANSITIONING DATA