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45
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65
–
Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
CLOCK INPUT OPERATING CONDITIONS
(Notes: 1
–
5, 15, 16, 30; notes appear on pages 50
–
53) (0
°
C
≤
T
A
≤
+ 70
°
C; V
DD
= +2.5V ±0.2V, V
DD
Q = +2.5V ±0.2V)
PARAMETER/CONDITION
Clock Input Mid-Point Voltage; CK and CK#
Clock Input Voltage Level; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Crossing Point Voltage; CK and CK#
SYMBOL
V
MP
(
DC
)
V
IN
(
DC
)
V
ID
(
DC
)
V
ID
(
AC
)
V
IX
(
AC
)
MIN
1.15
-0.3
0.36
0.7
MAX
1.35
UNITS
V
V
V
V
V
NOTES
6, 9
6
6, 8
8
9
V
DD
Q + 0.3
V
DD
Q + 0.6
V
DD
Q + 0.6
0.5 x V
DD
Q + 0.2
0.5 x V
DD
Q - 0.2
FIGURE 28 – SSTL_2 CLOCK INPUT
CK#
CK
2.80v
2
3
5
5
Maximum Clock Level
Minimum Clock Level
4
- 0.30v
1.25v
1.45v
1.05v
V
ID
(AC)
V
ID
(DC)
X
X
1
V
MP
(DC)
V
IX
(AC)
NOTE:
1. This provides a minimum of 1.15v to a maximum of 1.35v, and is always half of V
DD
Q.
2. CK and CK# must cross in this region.
3. CK and CK# must meet at least V
ID
(DC) min when static and is centered around V
MP
(DC)
4. CK and CK# must have a minimum 700mv peak to peak swing.
5. CK or CK# may not be more positive than V
DD
Q + 0.3v or more negative than Vss - 0.3v.
6. For AC operation, all DC clock requirements must also be satisfied.
7. Numbers in diagram reflect nominal values.
X
X