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參數(shù)資料
| 型號： | MT352CG |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | COFDM Demodulator |
| 中文描述： | COFDM解調(diào)器 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 478K |
| 代理商： | MT352CG |
MT352
Data Sheet
15
Zarlink Semiconductor Inc.
Note 1. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.
3.3 MPEG
3.3.1 Data Output Header Format
Figure 7 - DVB Transport Packet Header Byte
Parameter
Symbol
Value
Unit
Min.
Max.
CLK clock frequency (Primary)
f
CLK
t
BUFF
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU;DAT
t
R
t
F
t
SU;STO
0
450
kHz
Bus free time between a STOP and START condition
200
ns
Hold time (repeated) START condition
200
ns
LOW period of CLK clock
1300
ns
HIGH period of CLK clock
600
ns
Set-up time for a repeated START condition
200
ns
Data hold time (when input)
100
ns
Data set-up time
100
ns
Rise time of both CLK and DATA signal.
note 1
ns
Fall time of both CLK and DATA signals, (100 pF to ground)
20
ns
Set-up time for a STOP condition
200
ns
Table 2 - Timing of 2-Wire Bus
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT352CGGP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:COFDM Demodulator |
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| MT352CGGP2N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:COFDM Demodulator |
| MT352CGGP2Q | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:COFDM Demodulator |
| MT352GP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:COFDM Demodulator |
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