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參數(shù)資料
| 型號： | MT16LSDT6464AG-13E |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM MODULE |
| 中文描述： | 同步DRAM模塊 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 614K |
| 代理商： | MT16LSDT6464AG-13E |
256MB / 512MB (x64)
168-PIN SDRAM DIMMs
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
20
2002, Micron Technology Inc.
SPD EEPROM TIMING DIAGRAM
NOTE:
1. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
SCL
SDA IN
SDA OUT
tLOW
tSU:STA
tHD:STA
tF
tHIGH
tR
tBUF
tDH
tAA
tSU:STO
tSU:DAT
tHD:DAT
UNDEFINED
Table 21: Serial Presence-Detect EEPROM AC Operating Conditions
V
DD
= +3.3V ±0.3V; All voltages referenced to V
SS
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
SCL LOW to SDA data-out valid
t
AA
t
BUF
0.3
3.5
μs
Time the bus must be free before a new transition can
start
Data-out hold time
4.7
–
μs
t
DH
t
F
300
ns
SDA and SCL fall time
300
ns
Data-in hold time
t
HD:DAT
t
HD:STA
t
HIGH
t
I
t
LOW
t
R
f
SCL
t
SU:DAT
t
SU:STA
t
SU:STO
t
WRC
0
μs
Start condition hold time
4
μs
ClockHIGHperiod
4
μs
Noise suppression time constant at SCL, SDA inputs
100
ns
Clock LOW period
4.7
μs
SDA and SCL rise time
1
μs
SCL clock frequency
100
KHz
Data-in setup time
250
ns
Start condition setup time
4.7
μs
Stop condition setup time
4.7
μs
WRITE cycle time
10
ms
1
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