參數(shù)資料
型號(hào)： MT16LD1664AG-6X
廠商： Micron Technology, Inc.
英文描述： DRAM MODULE
中文描述： DRAM模塊
文件頁(yè)數(shù)： 13/27頁(yè)
文件大小： 518K
代理商： MT16LD1664AG-6X
13
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65
–
Rev. 2/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
(Notes: 1) (V
DD
= +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
SUPPLY VOLTAGE
V
DD
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
V
DD
x 0.7 V
DD
+ 0.5
V
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-1
V
DD
x 0.3
V
OUTPUT LOW VOLTAGE: I
OUT
= 3mA
V
OL
–
0.4
V
INPUT LEAKAGE CURRENT: V
IN
= GND to V
DD
I
LI
–
10
μA
OUTPUT LEAKAGE CURRENT: V
OUT
= GND to V
DD
I
LO
–
10
μA
STANDBY CURRENT:
SCL = SDA = V
DD
- 0.3V; All other inputs = GND or 3.3V +10%
I
SB
–
30
μA
POWER SUPPLY CURRENT:
SCL clock frequency = 100 KHz
I
CC
–
2
mA
SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS
(Notes: 1) (V
DD
= +3.3V ±0.3V)
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
SYMBOL
t
AA
t
BUF
t
DH
t
F
t
HD:DAT
t
HD:STA
t
HIGH
t
I
t
LOW
t
R
t
SCL
t
SU:DAT
t
SU:STA
t
SU:STO
t
WR
MIN
0.3
4.7
300
MAX
3.5
UNITS
μs
μs
ns
ns
μs
μs
μs
ns
μs
μs
KHz
ns
μs
μs
ms
NOTES
300
0
4
4
100
4.7
1
100
250
4.7
4.7
10
28
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