
MT1530 U
PSTREAM
A
MPLIFIER
A
DVANCE
D
ATA
S
HEET
CATV A
PPLICATIONS
DS-00010
Rev 1.2 — December 2000
Page 8 of 14
P
In addition to providing output power, the PA also plays a role in the gain-
programmability of the IC. The output amplifier has attenuation settings of 0, 6, and
12 dB. Higher attenuations reduce output power and noise. The programmed gain
control code automatically sets the PA’s attenuation. Gain control codes of 52
through 63 set the PA’s attenuation to 0 dB, putting the PA at maximum power. Gain
control codes of 46 to 51 set the PA’s attenuation to 6 dB, lowering its power by half.
Gain control codes of less than 46 set the PA’s attenuation to 12 dB, lowering its
power to one quarter of the maximum value. Transmit-disable and shutdown modes
turn off power to the PA for maximum isolation and minimum output noise.
8.2.4
PA CONTROL
The PA Control (PAC) both adjusts the output amp’s gain, and manages power-up
and power-down transients. The PAC uses internal timing circuits to control the
ramp-up and ramp-down of the PA’s bias block. This orderly ramp keeps the PA’s
output glitch to very low levels.
The PAC begins a bias ramp-down on the falling edge of TXEN. A rising TXEN
produces a bias ramp-up. Note that for a minimum glitch on the output, the rest of
the IC must already be powered up by having disabled shutdown mode.
8.3
SERIAL INTERFACE
The serial interface (SI) programs the gain of the MT1530 using an 8-bit control
word. The SI uses the gain control word to set the VA’s and PA’s gains individually
using an internal decoder. It has an active-low chip-select
(
CS
) to synchronize to
the incoming word. Data is clocked MSB first on the rising edge of SCLK. Data is
latched on the rising edge of
CS
. Table 4 and Table 5 show the register format.
Figure 13 illustrates serial interface timing.
Table 4
Serial Interface Control Word
B
IT
M
NEMONIC
D
ESCRIPTION
7 (MSB)
D7
Software shutdown (active low)
6
D6
Unused (Don’t Care)
5
D5
Gain control, Bit 5
4
D4
Gain control, Bit 4
3
D3
Gain control, Bit 3
2
D2
Gain control, Bit 2
1
D1
Gain control, Bit 1
0 (LSB)
D0
Gain control, Bit 0