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參數(shù)資料
| 型號： | MSTM-S3-TR-SS-077.76M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Stratum 3 Timing Module |
| 中文描述： | 層3定時模塊 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 1141K |
| 代理商： | MSTM-S3-TR-SS-077.76M |
Data Sheet #:
TM027 P
age
2
of
16
Rev:
P05
Date:
12 / 02 / 02
Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
General Description
The Connor-Winfield Stratum 3 Simplified Control Timing Mod-
ule acts as a complete system clock module for general Stratum
3 timing applications. The MSTM is designed to replace similar
units from TF Systems (TF118B) and Raltron (SY0001B).
Full external control input allows for selection and monitoring
of any of four possible operating states: 1) Holdover, 2) External
Reference #1, 3) External Reference #2, and 4) Free Run. Table
#1 illustrates the control signal inputs and corresponding opera-
tional states.
In the absence of External Control Inputs (A,B), the MSTM
enters the Free Run mode and signals an External Alarm. The
MSTM will enter other operating modes upon application of a
proper control signal. Mode 1 operation (A=1, B=0) results in an
output signal that is phase locked to the External Reference
Input #1. Mode 2 operation (A=0, B=1) results in an output sig-
nal that is phase locked to External Reference Input #2. Hold-
over mode operation (A=1, B=1) results in an output signal at or
near the frequency as determined by the latest (last) locked-
signal input values and the holdover performance of the MSTM.
Free Run ModeFree Run mode operation (A=0, B=0) is a guar-
anteed output of 4.6 ppm of the nominal frequency.
Alarm signals are generated at the Alarm Output during Hold-
over and Free Run operation. Alarm Signals are also generated
by Loss-of-Lock and Loss-of-Reference conditions. A high level
indicates an alarm condition. Real-time indication of the opera-
tional mode is available at unique operating mode outputs on
pins 1-4.
Control loop 0.1 Hz filters effectively attenuate any reference
jitter, smooth out phase transients, comply with wander transfer
and jitter tolerances.
Absolute Maximum Rating
Table 2
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
V
CC
V
I
T
s
Power Supply Voltage
-0.5
7.0
Volts
1.0
Input Voltage
-0.5
V
CC
+ 0.5
100
Volts
1.0
Storage Temperature
-55
deg. C
1.0
Functional Block Diagram
Figure 1
OCXO
Stratum3
FIFO
Holdover
DAC
Circuit
Phase
Build Out
Monitor
Tuning
Voltage
1
2
3
4
Free Run
Ref #1
Ref #2
Hold Over
CNTL A
CNTL B
Sync_Out
Ref
Control
Ex Ref 1
Ex Ref 2
PLL_TVL
Hold Over
Free Run
LOL & LOR
Alarm_Out
÷
N
DPLL
Reference
Clock
Opt_Out*
*Only one Opt_Out option is available per module
CNTL CNTL
A
Operational
Mode
Ref 1
Ref 2
Hold Over
Free Run PLL Unlock
Alarm Out
B
0
0
Free Run (Default Mode)
0
0
0
1
0
1
External Normal
Reference PLL_Unlock
#1 LOR
1
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
External Normal
Reference PLL_Unlock
#2 LOR
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
1
1
1
Hold Over
0
0
1
0
0
1
Function Control Table
Table 1
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