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參數(shù)資料
| 型號(hào)： | MSP50C614PJM |
| 廠(chǎng)商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 12.32 MHz, MIXED DSP, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 122K |
| 代理商： | MSP50C614PJM |
MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023C – DECEMBER 1999 – REVISED FEBRUARY 2001
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
dc electrical characteristics, TA = 0 to 70°C
PARAMETER
TEST CONDITIONS
MIN
TYP§
MAX
UNIT
Positive going threshold
2.4
VDD = 3 V
Negative going threshold
1.8
V
RESET
Threshold changes
Hysteresis
0.6
RESET
Threshold changes
Positive going threshold
3.3
VDD = 5.2 V
Negative going threshold
2.9
V
Hysteresis
0.4
High level input
VDD = 3 V
2
3
VIH
High-level input
voltage
VDD = 4.5 V
3
4.5
V
voltage
VDD = 5.2 V
3.5
5.2
Low level input
VDD = 3 V
0
1
VIL
Low-level input
voltage
VDD = 4.5 V
0
1.5
V
voltage
VDD = 5.2 V
0
1.7
IOH
High-level output
current per pin of I/O
port
VOH = 4 V
–2
mA
IOL
Low-level output
current per pin of I/O
port
VDD = 4.5 V
VOL = 0.5 V
5
mA
IOH (DAC)
High-level output
DAC current
VOH = 4 V
–10
mA
IOL (DAC)
Low-level output
DAC current
VOL = 0.5 V
20
mA
Ilkg
Input leakage
current
Excludes OSCIN
1
A
I(STANDBY)
Standby current
RESET is low
0.05
10
A
IDD
Operating current
VDD = 4.5 V,
FCLOCK = 12.32 MHz
15
mA
I(SLEEP-deep)
VDD = 4.5 V,
DAC off,
ARM set,
OSC disabled
0.05
10
I(SLEEP-mid)
Supply current
VDD = 4.5 V,
DAC off,
ARM set,
OSC enabled
40
60
A
I(SLEEP-light)
VDD = 4.5 V,
DAC off,
ARM clear,
OSC enabled
60
100
VIO
Input offset voltage
VDD = 4.5 V,
Vref = 1 to 4.25 V
25
50
mV
R(PULLUP)
F port pullup
resistance
VDD = 5 V
70
150
k
f(RTO t i )
Trim deviation
RRTO = 470 k, VDD = 4.5 V, TA = 25°C,
±1%
±3%
f(RTO-trim)
Trim deviation
fRTO = 8.192 MHz (PLL setting = 7 Ch)
±1%
±3%
f(RTO lt)
Voltage deviation
RRTO = 470 k, VDD = 3.5 to 5.2 V,
TA = 25°C,
±15%
f(RTO-volt)
Voltage deviation
fRTO = 8.192 MHz (PLL setting = 7 Ch)
±1.5%
f(RTO t
)
Temperature
RRTO = 470 k, VDD = 4.5 V, TA = 0 to 70°C,
±003
%/
°C
f(RTO-temp)
deviation
fRTO = 8.192 MHz (PLL setting = 7 Ch)
±0.03
%/
°C
f(RTO
)
Resistance deviation
VDD = 4.5 V,
TA = 25°C,
R(OSC) = 470 k at ± 1%,
±1%
f(RTO-res)
Resistance deviation
fRTO = 8.192 MHz (PLL setting = 7 Ch)
±1%
Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output
and other outputs are open circuited.
The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored.
§ Typical voltage and current measurement taken at 25
°C
Cannot exceed 15 mA total per internal VDD pin. Port A, B share 1 internal VDD pin; Port C, D share 1 internal VDD.
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