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參數(shù)資料
| 型號： | MSP50C605PJM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 12.32 MHz, MIXED DSP, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 121K |
| 代理商： | MSP50C605PJM |
MSP50C605
MIXED-SIGNAL PROCESSOR
SPSS025B– FEBRUARY 2000 – REVISED FEBRUARY 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
NAME
PIN NO.
PAD NO.
I/O
DESCRIPTION
Input/Output Ports
PC0 – PC7
89 – 82
8 – 1
I/O
Port C general-purpose I/O
(1 Byte)
PD0 – PD7
99 – 92
18 – 11
I/O
Port D general-purpose I/O
(1 Byte)
PE0 – PE7
46 – 39
48 – 41
I/O
Port E general-purpose I/O
(1 Byte)
PF0 – PF7
16 – 9
31 – 24
I
Port F key-scan input
(1 Byte)
Pins PD4 and PD5 may be dedicated to the comparator function, if the comparator enable bit is set.
Refer to Section 3.3, Comparator, for details.
Scan Port Control Signals
SCANIN
37
39
I
Scan port data input
SCANOUT
33
35
O
Scan port data output
SCANCLK
36
38
I
Scan port clock
SYNC
35
37
I
Scan port synchronization
TEST
34
36
I
C605: test modes
The scan port pins must be bonded out on any MSP50C605 production board.
Consult the Important Note regarding Scan Port Bond Out, see Chapter 7 in the MSP50C614 User’s Guide (SPSU014).
Reference Oscillator Signals
OSCOUT
49
51
O
Resistor/crystal reference out
OSCIN
48
50
I
Resistor/crystal reference in
PLL
47
49
O
Phase-lock-loop filter
Digital-to-Analog Sound Output
DACP
7
22
O
Digital-to-analog plus output (+)
DACM
5
20
O
Digital-to-analog minus output (–)
Initialization
RESET
38
40
I
Initialization
Power Signals
VSS
17, 50, 90,
100
32, 52, 9,
19
Ground
VDD
6, 8, 31,
32, 91
21, 23,
33, 34, 10
Processor power (+)
The VSS and VDD connections service the DACcircuitry.Theirpinstendtosustainahighercurrentdraw.Adedicateddecouplingcapacitoracross
these pins is therefore required.
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