參數(shù)資料
型號： MSP430G2533IRHB32T
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQCC32
封裝： GREEN, PLASTIC, QFN-32
文件頁數(shù)： 22/63頁
文件大?。?/td> 831K
代理商： MSP430G2533IRHB32T
t
SU,MI
t
HD,MI
UCLK
SOMI
SIMO
t
VALID,MO
t
HD,MO
CKPL = 0
CKPL = 1
t
LO/HI
t
LO/HI
1/f
UCxCLK
t
SU,MI
t
HD,MI
UCLK
SOMI
SIMO
t
VALID,MO
CKPL = 0
CKPL = 1
1/f
UCxCLK
t
HD,MO
t
LO/HI
t
LO/HI
MSP430G2x33
MSP430G2x03
SLAS734C
– APRIL 2011 – REVISED AUGUST 2011
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fUSCI
USCI input clock frequency
SMCLK, duty cycle = 50%
± 10%
fSYSTEM
MHz
Maximum BITCLK clock frequency
fmax,BITCLK
3 V
2
MHz
(equals baudrate in MBaud)(1)
tτ
UART receive deglitch time(2)
3 V
50
100
600
ns
(1)
The DCO wake-up time must be considered in LPM3/4 for baud rates above 1 MHz.
(2)
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 16 and
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fUSCI
USCI input clock frequency
SMCLK, duty cycle = 50%
± 10%
fSYSTEM
MHz
tSU,MI
SOMI input data setup time
3 V
75
ns
tHD,MI
SOMI input data hold time
3 V
0
ns
tVALID,MO
SIMO output data valid time
UCLK edge to SIMO valid, CL = 20 pF
3 V
20
ns
Figure 16. SPI Master Mode, CKPH = 0
Figure 17. SPI Master Mode, CKPH = 1
Copyright
2011, Texas Instruments Incorporated
29
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