參數(shù)資料
型號(hào)： MSP430G2101IRSA16T
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, RISC MICROCONTROLLER, PQCC16
封裝： GREEN, PLASTIC, QFN-16
文件頁數(shù)： 45/48頁
文件大?。?/td> 1094K
代理商： MSP430G2101IRSA16T
MSP430G2x11
MSP430G2x01
SLAS695D
– FEBRUARY 2010 – REVISED FEBRUARY 2011
Table 2. Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
14
16
N, PW
RSA
P1.0/
General
–purpose digital I/O pin
TA0CLK/
Timer0_A, clock signal TACLK input
2
1
I/O
ACLK/
ACLK signal output
CA0
Comparator_A+, CA0 input(1)
P1.1/
General
–purpose digital I/O pin
TA0.0/
3
2
I/O
Timer0_A, capture: CCI0A input, compare: Out0 output
CA1
Comparator_A+, CA1 input(1)
P1.2/
General
–purpose digital I/O pin
TA0.1/
4
3
I/O
Timer0_A, capture: CCI1A input, compare: Out1 output
CA2
Comparator_A+, CA2 input(1)
P1.3/
General
–purpose digital I/O pin
CA3/
5
4
I/O
Comparator_A+, CA3 input(1)
CAOUT
Comparator_A+, output(1)
P1.4/
General
–purpose digital I/O pin
SMCLK/
SMCLK signal output
6
5
I/O
CA4/
Comparator_A+, CA4 input(1)
TCK
JTAG test clock, input terminal for device programming and test
P1.5/
General
–purpose digital I/O pin
TA0.0/
Timer0_A, compare: Out0 output
7
6
I/O
CA5/
Comparator_A+, CA5 input(1)
TMS
JTAG test mode select, input terminal for device programming and test
P1.6/
General
–purpose digital I/O pin
TA0.1/
Timer0_A, compare: Out1 output
8
7
I/O
CA6/
Comparator_A+, CA6 input(1)
TDI/TCLK
JTAG test data input or test clock input during programming and test
P1.7/
General
–purpose digital I/O pin
CA7/
CA7 input(1)
9
8
I/O
CAOUT/
Comparator_A+, output(1)
TDO/TDI(2)
JTAG test data output terminal or test data input during programming and test
XIN/
Input terminal of crystal oscillator
P2.6/
13
12
I/O
General
–purpose digital I/O pin
TA0.1
Timer0_A, compare: Out1 output
XOUT/
Output terminal of crystal oscillator(3)
12
11
I/O
P2.7
General
–purpose digital I/O pin
RST/
Reset
NMI/
10
9
I
Nonmaskable interrupt input
SBWTDIO
Spy
–Bi–Wire test data input/output during programming and test
TEST/
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
11
10
I
SBWTCK
Spy
–Bi–Wire test clock input during programming and test
DVCC
1
16
NA
Supply voltage
DVSS
14
NA
Ground reference
NC
-
15
NA
Not connected
QFN Pad
-
Pad
NA
QFN package pad connection to VSS recommended.
(1)
MSP430G2x11 only
(2)
TDO or TDI is selected via JTAG instruction.
(3)
If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
6
2010–2011, Texas Instruments Incorporated
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