參數(shù)資料
型號(hào)： MSP430CG4616IZQW
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PBGA113
封裝： PLASTIC, BGA-113
文件頁(yè)數(shù)： 51/110頁(yè)
文件大?。?/td> 1605K
代理商： MSP430CG4616IZQW
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I APRIL 2006 REVISED MARCH 2011
45
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fUSCI
USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50%
± 10%
fSYSTEM
MHz
fBITCLK
BITCLK clock frequency
(equals Baudrate in MBaud)
2.2V /3 V
1
MHz
t
UART receive deglitch time
2.2 V
50
150
600
ns
tτ
UART receive deglitch time
(see Note 1)
3 V
50
100
600
ns
NOTE 1: Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI master mode) (see Figure 18 and Figure 19)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fUSCI
USCI input clock frequency
SMCLK, ACLK
Duty Cycle = 50%
± 10%
fSYSTEM
MHz
t
SOMI input data setup time
2.2 V
110
ns
tSU,MI
SOMI input data setup time
3 V
75
ns
t
SOMI input data hold time
2.2 V
0
ns
tHD,MI
SOMI input data hold time
3 V
0
ns
t
SIMO output data valid time
UCLK edge to SIMO valid;
2.2 V
30
ns
tVALID,MO
SIMO output data valid time
UCLK edge to SIMO valid;
CL = 20 pF
3 V
20
ns
USCI (SPI slave mode) (see Figure 20 and Figure 21)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time
STE low to clock
2.2 V/3 V
50
ns
tSTE,LAG
STE lag time
Last clock to STE high
2.2 V/3 V
10
ns
tSTE,ACC
STE access time
STE low to SOMI data out
2.2 V/3 V
50
ns
tSTE,DIS
STE disable time
STE high to SOMI high impedance
2.2 V/3 V
50
ns
t
SIMO input data setup time
2.2 V
20
ns
tSU,SI
SIMO input data setup time
3 V
15
ns
t
SIMO input data hold time
2.2 V
10
ns
tHD,SI
SIMO input data hold time
3 V
10
ns
t
SOMI output data valid time
UCLK edge to SOMI valid;
2.2 V
75
110
ns
tVALID,SO
SOMI output data valid time
UCLK edge to SOMI valid;
CL = 20 pF
3 V
50
75
ns
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