參數(shù)資料
型號(hào)： MSP34X5G
廠商： Electronic Theatre Controls, Inc.
英文描述： MSP 34x5G Multistandard Sound Processor Family
中文描述： 中型34x5G多標(biāo)準(zhǔn)聲音處理器系列
文件頁數(shù)： 13/98頁
文件大?。?/td> 1541K
代理商： MSP34X5G
PRELIMINARY DATA SHEET
MSP 34x5G
Micronas
13
2.6. SCART Signal Routing
2.6.1. SCART DSP In and SCART Out Select
The SCART DSP Input Select and SCART Output
Select blocks include full matrix switching facilities. To
design a TV set with two pairs of SCART-inputs and
one pair of SCART-outputs, no external switching
hardware is required. The switches are controlled by
the ACB user register (see page 34).
2.6.2. Stand-by Mode
If the MSP 34x5G is switched off by first pulling
STANDBYQ low and then (after >1
μ
s delay) switching
off DVSUP and AVSUP, but keeping AHVSUP
(
‘
Stand-by
’
-mode
), the SCART switches maintain
their position and function. This allows the copying
from selected SCART-inputs to SCART-outputs in the
TV set
’
s stand-by mode.
In case of power on or starting from stand-by (switch-
ing on the DVSUP and AVSUP, RESETQ going high
2 ms later), all internal registers except the ACB regis-
ter (page 34) are reset to the default configuration (see
Table 3
–
5 on page 18). The reset position of the ACB
register becomes active after the first I
2
C transmission
into the Baseband Processing part. By transmitting the
ACB register first, the reset state can be redefined.
2.7. I
2
S Bus Interface
The MSP 34x5G has a synchronous master/slave
input/output interface running on 32 kHz.
The interface accepts two formats:
1. I
2
S_WS changes at the word boundary
2. I
2
S_WS changes one I
2
S-clock period before the
word boundaries.
All I
2
S options are set by means of the MODUS and
the I2S_CONFIG registers.
The I
2
S bus interface consists of five pins:
–
I2S_DA_IN1, I2S_DA_IN2:
I
2
S serial data input: 16, 18....32 bits per sample
–
I2S_DA_OUT:
I
2
S serial data output: 16, 18...32 bits per sample
–
I2S_CL:
I
2
S serial clock
–
I2S_WS:
I
2
S word strobe signal defines the left and right
sample
If the MSP 34x5G serves as the master on the I
2
S
interface, the clock and word strobe lines are driven by
the IC. In this mode, only 16 or 32 bits per sample can
be selected. In slave mode, these lines are input to the
IC and the MSP clock is synchronized to 576 times the
I2S_WS rate (32 kHz). NICAM operation is not possi-
ble in slave mode.
An I
2
S timing diagram is shown in Fig. 4
–
28 on
page 63.
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