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| 型號： | MSP3430 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Multistandard Sound Processor Family |
| 中文描述： | 多標準聲音處理器系列 |
| 文件頁數(shù)： | 14/101頁 |
| 文件大?。?/td> | 752K |
| 代理商： | MSP3430 |
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MSP 34x0G
PRELIMINARY DATA SHEET
14
Micronas
2.7. I
2
S Bus Interface
The MSP 34x0G has a synchronous master/slave
input/output interface running on 32 kHz.
The interface accepts two formats:
1. I
2
S_WS changes at the word boundary
2. I
2
S_WS changes one I
2
S-clock period before the
word boundaries.
All I
2
S options are set by means of the MODUS and
the I2S_CONFIGURATION registers.
The I
2
S bus interface consists of five pins:
–
I2S_DA_IN1, I2S_DA_IN2:
I
2
S serial data input: 16, 18....32 bits per sample
–
I2S_DA_OUT:
I
2
S serial data output: 16, 18...32 bits per sample
–
I2S_CL:
I
2
S serial clock
–
I2S_WS:
I
2
S word strobe signal defines the left and right
sample
If the MSP 34x0G serves as the master on the I
2
S
interface, the clock and word strobe lines are driven by
the IC. In this mode, only 16 or 32 bits per sample can
be selected. In slave mode, these lines are input to the
IC and the MSP clock is synchronized to 576 times the
I2S_WS rate (32 kHz). NICAM operation is not possi-
ble in slave mode.
An I
2
S timing diagram is shown in Fig. 4
–
28 on
page 67.
2.8. ADR Bus Interface
For the ASTRA Digital Radio System (ADR), the
MSP 3400G, MSP 3410G, and MSP 3450G performs
preprocessing such as carrier selection and filtering.
Via the 3-line ADR-bus, the resulting signals are trans-
ferred to the DRP 3510A coprocessor, where the
source decoding is performed. To be prepared for an
upgrade to ADR with an additional DRP board, the fol-
lowing lines of MSP 34x0G should be provided on a
feature connector:
–
AUD_CL_OUT
–
I2S_DA_IN1 or I2S_DA_IN2
–
I2S_DA_OUT
–
I2S_WS
–
I2S_CL
–
ADR_CL, ADR_WS, ADR_DA
For more details, please refer to the DRP 3510A data
sheet.
2.9. Digital Control I/O Pins and
Status Change Indication
The static level of the digital input/output pins
D_CTR_I/O_0/1 is switchable between HIGH and
LOW via the I
2
C-bus by means of the ACB register
(see page 39). This enables the controlling of external
hardware switches or other devices via I
2
C-bus.
The digital input/output pins can be set to high imped-
ance by means of the MODUS register (see page 24).
In this mode, the pins can be used as input. The cur-
rent state can be read out of the STATUS register (see
page 26).
Optionally, the pin D_CTR_I/O_1 can be used as an
interrupt request signal to the controller, indicating any
changes in the read register STATUS. This makes poll-
ing unnecessary, I
2
C bus interactions are reduced to a
minimum (see STATUS register on page 26 and
MODUS register on page 24).
2.10. Clock PLL Oscillator and Crystal Specifications
The MSP 34x0G derives all internal system clocks
from the 18.432 MHz oscillator. In NICAM or in I
2
S-
Slave mode, the clock is phase-locked to the corre-
sponding source. Therefore, it is not possible to use
NICAM and I
2
S-Slave mode at the same time.
For proper performance, the MSP clock oscillator
requires a 18.432 MHz crystal. Note that for the
phase-locked modes (NICAM, I
2
S-Slave), crystals with
tighter tolerance are required.
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相關代理商/技術參數(shù) |
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