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參數(shù)資料
| 型號(hào)： | MSM98S000 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 0.8m Mixed 3-V/5-V Sea of Gates and Customer Structured Arrays |
| 中文描述： | 0.8混合3-V/5-V海蓋茨和客戶結(jié)構(gòu)陣列 |
| 文件頁數(shù)： | 6/23頁 |
| 文件大?。?/td> | 96K |
| 代理商： | MSM98S000 |
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MSM38S/98S Data Sheet
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4
OKI SEMICONDUCTOR
- Add together all the area occupied by the required random logic and macrocells and select
the optimum array.
2. Make a floor plan for the design’s megacells.
- OKI Design Center engineers verify the master slice and review simulation.
- OKI Design Center engineers floorplan the array using OKI’s proprietary floorplanner and
customer performance specifications.
- Using OKI CAD software, Design Center engineers remove the SOG transistors and replace
them with diffused memory macrocells to the customer’s specifications.
Figure 2
shows an array base after placement of the optimized memory macrocells.
Figure 2. Optimized Memory Macrocell Floor Plan
3. Place and route logic into the array transistors.
- OKI Design Center engineers use layout software and customer performance specifications
to connect the random logic and optimized memory macrocells.
Figure 3
marks the area in which placement and routing is performed with light shading.
Figure 3. Random Logic Place and Route
Mega macrocell
Early mask high-density ROM
High-density RAM
Multi-port RAM
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