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參數(shù)資料
| 型號： | MSM82C37B-5RS |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | DMA控制器 |
| 英文描述： | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 16/34頁 |
| 文件大小： | 327K |
| 代理商： | MSM82C37B-5RS |
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Semiconductor
MSM82C37B-5RS/GS/VJS
Mode Register
Each channel is equipped with a 6-bit write-only mode register, which is decided by setting DB0,
DB1 which channel is to be written when writing from CPU is programming status. The bit
description is outlined in Figure 4.
This register is not cleared by Reset or Master Clear instruction.
DB7
00: Channel 0 Selected
01: Channle 1 Selected
10: Channel 2 Selected
11: Channle 3 Selected
DB6
DB5
DB4
DB3
DB2
DB1
DB0
00: Verify Transfer
01: Write Transfer
10: Read Transfer
11: Disabled
(Invalid When DB6DB7 = "11")
0: Auto Initialize Disabled
1: Auto Initialize Enabled
0: Address Increment (+1) Selected
1: Address Decrement (–1) Selected
00: Demand Transfer Mode Selected
01: Single Transfer Mode Selected
10: Block Transfer Mode Selected
11: Cascade Mode Selected
Figure 4 Mode Register
Request Register
In addition to using the DREQ signal, the MSM82C37B-5 can request DMA transfers by software
means. This involves setting the request bit of request register. Each channel has a corresponding
request bit in the request register, and the order of priority of these bits is determined by the
priority decision circuit irrespective of the mask register. DMA transfers are acknowledged in
accordance with the decided order of priority.
All request bits are reset when the TC is reached, and when the request bit of a certain channel
has been received, all other request bits are cleared. When a memory-memory transfer is
commenced, the channel 0 request bit is set. The bit description is outlined in Figure 5.
DB7
00: Channel 0 Selected
01: Channel 1 Selected
10: Channel 2 Selected
11: Channel 3 Selected
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0: Request Bit Cleared
1: Request Bit Set
Not Used
Figure 5 Request Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM82C37B-5GS-2K | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PQFP44 |
| MSM82C43GS-K | 20 I/O, PIA-GENERAL PURPOSE, PDSO24 |
| MSM82C51A-2GS | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32 |
| MSM82C54-2GS-K | 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32 |
| MSM82C54-2RS | 3 TIMER(S), PROGRAMMABLE TIMER, PDIP24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM82C37B-5VJS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE DMA CONTROLLER |
| MSM82C43 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
| MSM82C51A-2GS-K | 制造商:OK International 功能描述:USART, 32 Pin, Plastic, SOP 制造商:OKI Semiconductor 功能描述:USART, 32 Pin, Plastic, SOP |
| MSM82C51A-2JS | 制造商:ROHM Semiconductor 功能描述: |
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