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MSM66573 Family User's Manual
Chapter 8 General-Purpose 8/16 Bit Timers
55H
FEH
FFH
55H
56H
Interrupt request generated
CPUCLK
TM count CLK
(1/8 TBCCLK)
TM6R
TM6C
Overflow signal
8.8.4 Timer 6 Operation
Auto-reload timer mode
When the MODWDT bit in TM6CON is reset to "0", the mode changes to the auto-reload
timer mode. If the ATMRUN bit is set to "1", timer 6 will begin counting upward, running on
the count clock selected by TM6CON. When TM6C overflows, an interrupt request is
generated and the contents of TM6R are loaded into TM6C. This operation is repeated until
the ATMRUN bit is reset to "0". Figure 8-15 shows an operation example (for settings of
1/n counter frequency division ratio 1/1 and 1/8 TBCCLK).
Figure 8-15 Timer 6 Operation (During Auto-Reload Timer Mode)
Watchdog timer (WDT) mode
When the MODWDT bit in TM6CON is set to "1", the mode changes to the WDT mode.
Once the WDT mode is set, it is not possible to return to the auto-reload timer mode until
the system is reset. In the WDT mode, writing "n3H" to TM6C will cause the WDT count
operation to begin. Thereafter, alternately writing "nCH" and "n3H" by the program will
cause the contents of TM6R to be loaded into TM6C and initialize WDT.
If WDT initialization is not implemented within the fixed amount of time set by the count clock
and the reload value, then TM6C will overflow and the system will be reset. To process a
system reset, the branch address (2 bytes) stored in addresses 0004 to 0005 (vector
address for reset by WDT) is loaded into the program counter.
The time (tWDT) until TM6C overflows can be expressed by the below equation, where f
[MHz] is the fundamental clock (CPUCLK), T is the TM6C count clock (divided value of
TBCCLK), n is the divisor for the 1/n counter at the TBC front stage, and R is the value of
TM6R.
tWDT = (1/f) T n (256 – R) [ms] (R: 0 to 255)
Figure 8-16 shows timing diagrams of an out-of-control program and detection by WDT.
Figure 8-17 shows an example of an out-of-control program.