參數(shù)資料
型號: MSM38S0000
廠商: Electronic Theatre Controls, Inc.
英文描述: 0.8m Mixed 3-V/5-V Sea of Gates and Customer Structured Arrays
中文描述: 0.8混合3-V/5-V海蓋茨和客戶結(jié)構(gòu)陣列
文件頁數(shù): 5/23頁
文件大小: 96K
代理商: MSM38S0000
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I
MSM38S/98S Data Sheet
I
3
OKI SEMICONDUCTOR
ARRAY ARCHITECTURE
The primary components of a 0.8μm MSM38S/ 98S circuit include:
I/ O base cells
Configurable I/ O pads for V
DD
, V
SS
, or I/ O (I/ O in both 3V and 5V)
V
DD
and V
SS
pads dedicated to wafer probing
Separate power bus for output buffers
Separate power bus for internal core logic and input buffers
Core base cells containing N-channel and P-channel pairs, arranged in column of gates
Isolated gate structure for reduced input capacitance and increased routing flexibility
Each array has 16 dedicated corner pads for power and ground use during wafer probing, with four pads
per corner. The arrays also have separate power rings for the internal core functions (V
DDC
and V
SSC
) and
output drive transistors (V
DDO
for 3 V and V
SSO
).
Figure 1. MSM38S/98S Array Architecture
MSM98S000 CSA Layout Methodology
The procedure to design, place, and route a CSA follows.
1. Select suitable base array frame from the available predefined sizes. To select an array size:
- Identify the macrocell functions required and the minimum array size to hold the macrocell
functions.
Four-transistor
basic core cell
Separate power bus over
I/O cell for output buffers
(V
DDO
(3.3 V), V
DDO
(5 V), V
SSO
)
V
, V
pads in
each corner for
wafer probing only
Configurable I/O pads for
V
(3.3 V), V
(5 V), V
SS
,
I/O (3.3 V), or I/O (5 V)
Separate power bus
for internal core logic
I/O cells include
level shifter
V
SSO
V
DDO
(3.3 V)
V
DDO
(5 V)
Column
of Gates
Core Area
V
DD
= 3.3 or 5 V
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