參數(shù)資料
型號(hào): MSK4400
廠商: MS KENNEDY CORP
元件分類: 運(yùn)動(dòng)控制電子
英文描述: 10 Amp, 75V, 3 Phase MOSFET Bridge with Intelligent Integrated Gate Drive(10A,75V,3相位MOSFET橋驅(qū)動(dòng)器(帶智能門驅(qū)動(dòng)控制電路))
中文描述: AC MOTOR CONTROLLER, 25 A, UFM20
文件頁數(shù): 3/5頁
文件大小: 254K
代理商: MSK4400
APPLICATION NOTES
MSK 4400 PINOUT DESCRIPTIONS
A, B, C -
Are the connections to the motor phase
windings from the bridge output. The wiring to these
pins should be sized according to the required current
by the motor. There are no short circuit provisions for
these outputs. Shorts to V+ or gound from these pins
must be avoided or the bridge will be destroyed.
3
Rev. D 6/00
AL, BL, CL -
Are the logic level inputs for controlling
the low side switch for each of the three phases. A
logic HIGH turns the low side output on, sinking the
output current and pulling it down. If the correspond-
ing high side switch is ON, the device will turn off the
high side output, insert the dead time and then com-
mand the lowside output on. The low side input has
priority over the high side input.
AH, BH, CH -
Are the logic level inputs for controlling
the high side switch for each of the three phases. A
logic low turns the high side output ON, sourcing the
output current and pulling it up. If the corresponding
low side switch is ON, the device will ignore the high
side input until the lowside is turned off and dead time
has elapsed. Again, the lowside input has priority.
AV+,BV+,CV+ -
Are the power connections from the
hybrid to the bus. The pins for each phase are brought
out separately and must be connected together to the
V+ source externally. The external wiring to these pins
should be sized according to the RMS current required
by the motor. These pins should be bypassed by a high
quality monolithic ceramic capacitor for high frequen-
cies and enough bulk capacitance for keeping the
V+supply from drooping. 1000
μ
F of bulk capacitance
was used in the test circuit. The voltage range on these
pins is from 16 volts up to 75 volts.
RS
ENSE
-
Is the connection point for the bottom of the
three phse bridge. A low value resistor between here
and the GND will produce a voltage proportional to cur-
rent in the bridge. Both pins must be connected. If a
resistor is not used, these pins must be connected to
GND.
EN -
Is the Logic level input for enabling and disabling
the bridge outputs. A logic low enables output switch-
ing.
GND -
Is the logic input return connection, the VBIAS
return and the V+ return.
SWR -
Is the control for the amount of dead time be-
tween a high side switch ON and the corresponding
low side switch OFF and vice versa. Leaving it open
creates the most dead time, while connecting a 12 K
resistor to VBIAS creates the least.
VBIAS -
Is the supply voltage for running all of the
low level logic and gate drive functions.This pin should
be bypassed to GND using a 0.1
μ
F ceramic capacitor
and a 4.7μF bulk capacitor.
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