參數(shù)資料
型號(hào)： MSC8144VT1000A
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 61/80頁(yè)
文件大?。?/td> 0K
描述： IC DSP QUAD 1GHZ 783FCPBGA
標(biāo)準(zhǔn)包裝： 1
系列： StarCore
類(lèi)型： SC3400 內(nèi)核
接口： 以太網(wǎng)，I²C，SPI，TDM，UART，UTOPIA
時(shí)鐘速率： 1.0GHz
非易失內(nèi)存： 外部
芯片上RAM： 10.5MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.00V
工作溫度： 0°C ~ 90°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤(pán)
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
64
Figure 40 shows the test access port timing diagram
Figure 41 shows the TRST timing diagram.
3
Hardware Design Considerations
The following sections discuss areas to consider when the MSC8144 device is designed into a system.
3.1
3.1.1
Power-on Sequence
Use the following guidelines for power-on sequencing:
There are no dependencies in power-on/power-off sequence between VDDM3 and VDD supplies.
There are no dependencies in power-on/power-off sequence between RapidIO supplies: VDDSXC, VDDSXP,
VDDRIOPLL and other MSC8144 supplies.
VDDPLL should be coupled with the VDD power rail with extremely low impedance path.
External voltage applied to any input line must not exceed the related to this port I/O supply by more than 0.6 V at any time,
including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for
configuration purposes. This is an acceptable exception to the rule during start-up. However, each such input can draw up to 80
mA per input pin per MSC8144 device in the system during start-up. An assertion of the inputs to the high voltage level before
power-up should be with slew rate less than 4 V/ns.
Figure 40. Test Access Port Timing
Figure 41. TRST Timing
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
Input Data Valid
Output Data Valid
TMS
tTDIVKH
tTDIXKH
tTDOHOV
tTDOHOZ
TRST
(Input)
tTRST
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