參數(shù)資料
型號(hào): MSC8144SVT800A
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 44/80頁(yè)
文件大?。?/td> 0K
描述: IC DSP QUAD 800MHZ 783FCBGA
標(biāo)準(zhǔn)包裝: 1
系列: StarCore
類(lèi)型: SC3400 內(nèi)核
接口: 以太網(wǎng),I²C,SPI,TDM,UART,UTOPIA
時(shí)鐘速率: 800MHz
非易失內(nèi)存: 外部
芯片上RAM: 10.5MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.00V
工作溫度: 0°C ~ 105°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤(pán)
Electrical Characteristics
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
49
2.6.5.6
Receiver Eye Diagrams
For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the corresponding bit error rate
specification (Table 32, Table 33, and Table 34) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter)
falls entirely within the unshaded portion of the receiver input compliance mask shown in Figure 14 with the parameters
specified in Table 35. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the
device replaced with a 100
Ω ±5% differential resistive load.
2.6.5.7
Measurement and Test Requirements
Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE Std.
802.3ae-2002, the measurement and test requirements defined here are similarly guided by Clause 47. In addition, the CJPAT
test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter
measurements. Annex 48B of IEEE Std. 802.3ae-2002 is recommended as a reference for additional information on jitter test
methods.
Figure 14. Receiver Input Compliance Mask
Table 35. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
Receiver Type
VDIFFmin (mV)
VDIFFmax (mV)
A (UI)
B (UI)
1.25 GBaud
100
800
0.275
0.400
2.5 GBaud
100
800
0.275
0.400
3.125 GBaud
100
800
0.275
0.400
1
0
VDIFF max
–VDIFF max
VDIFF min
–VDIFF min
Time (UI)
R
e
ce
iv
er
D
if
fe
rent
ial
Inp
u
tV
o
lt
age
0
A
B
1 – B
1 – A
相關(guān)PDF資料
PDF描述
MSC8144SVT1000A IC DSP QUAD 1GHZ 783FCPBGA
KMC8113TVT4800V IC DSP 300/400MHZ 431FCPGA
ECS-H1DY684R CAP TANT 0.68UF 20V 20% 1206
TAJC107M010K CAP TANT 100UF 10V 20% 2312
GEC10DREN-S734 CONN EDGECARD 20POS .100 EYELET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSC8144SVT800B 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144TVT1000A 功能描述:IC DSP QUAD 1GHZ 783FCPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號(hào)處理器) 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類(lèi)型:定點(diǎn) 接口:I²C,McASP,McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類(lèi)型:表面貼裝 封裝/外殼:548-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA(27x27) 包裝:托盤(pán) 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
MSC8144TVT1000B 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144TVT800A 功能描述:IC DSP QUAD 800MHZ 783FCBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號(hào)處理器) 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類(lèi)型:定點(diǎn) 接口:I²C,McASP,McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類(lèi)型:表面貼裝 封裝/外殼:548-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA(27x27) 包裝:托盤(pán) 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
MSC8144TVT800B 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA