參數資料
型號: MSC8112TMP2400V
廠商: Freescale Semiconductor
文件頁數: 18/44頁
文件大?。?/td> 0K
描述: DSP DUAL CORE 431-FCPBGA
標準包裝: 60
系列: StarCore
類型: SC140 內核
接口: 以太網,I²C,TDM,UART
時鐘速率: 300MHz
非易失內存: 外部
芯片上RAM: 448kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.10V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 431-BFBGA,FCBGA
供應商設備封裝: 431-FCPBGA(20x20)
包裝: 托盤
Electrical Characteristics
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
25
2.5.5.2
CLKIN to CLKOUT Skew
Table 17 describes the CLKOUT-to-CLKIN skew timing.
For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 16 to adjust the rise-to-fall timing
values specified for CLKIN synchronization. Figure 12 shows the relationship between the CLKOUT and CLKIN timings.
2.5.5.3
DMA Data Transfers
Table 17 describes the DMA signal timing.
The DREQ
signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ
according to the timings in Table 17. Figure 13 shows synchronous peripheral interaction.
Table 16. CLKOUT Skew
No.
Characteristic
Min1
Max1
Units
20
Rise-to-rise skew
0.0
0.95
ns
21
Fall-to-fall skew
–1.5
1.0
ns
24
CLKOUT phase (1.1 V, 100 MHz)
Phase high
Phase low
3.3
ns
Notes:
1.
A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.
2.
Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.
3.
CLKOUT skews are measured using a load of 10 pF.
4.
CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.
Figure 12. CLKOUT and CLKIN Signals.
Table 17. DMA Signals
No.
Characteristic
Ref = CLKIN
Units
Min
Max
37
DREQ set-up time before the 50% level of the falling edge of REFCLK
5.0
ns
38
DREQ hold time after the 50% level of the falling edge of REFCLK
0.5
ns
39
DONE set-up time before the 50% level of the rising edge of REFCLK
5.0
ns
40
DONE hold time after the 50% level of the rising edge of REFCLK
0.5
ns
41
DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge
0.5
7.5
ns
CLKIN
CLKOUT
20
21
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