參數(shù)資料
型號: MSC7116VF1000
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 266 MHz, OTHER DSP, PBGA400
封裝: 17 X 17 MM, MAPBGA-400
文件頁數(shù): 31/60頁
文件大?。?/td> 1566K
代理商: MSC7116VF1000
MSC7116 Data Sheet, Rev. 13
Freescale Semiconductor
37
2.5.9
UART Timing
2.5.10
EE Timing
Figure 24 shows the signal behavior of the EE pin.
Table 27. UART Timing
No.
Characteristics
Expression
Min
Max
Unit
Internal bus clock (APBCLK)
FCORE/2
133
MHz
Internal bus clock period (1/APBCLK)
TAPBCLK
7.52
ns
400
URXD and UTXD inputs high/low duration
16
× TAPBCLK
120.3
ns
401
URXD and UTXD inputs rise/fall time
5
ns
402
UTXD output rise/fall time
5
ns
Figure 21. UART Input Timing
Figure 22. UART Output Timing
Table 28. EE0 Timing
Number
Characteristics
Type
Min
65
EE0 input to the core
Asynchronous
4 core clock periods
66
EE0 output from the core
Synchronous to core clock
1 core clock period
Notes:
1.
The core clock is the SC1400 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
2.
Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1400 Core Reference Manual for details.
3.
Refer to Table 1-11 on page 1-16 for details on EE pin functionality.
Figure 23. EE Pin Timing
UTXD, URXD
400
inputs
400
401
UTXD Output
402
EE0 In
65
EE0 Out
66
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC7116VF1000,
MSC7116VM1000,
MSC711XADS
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