參數(shù)資料
型號: MSC7115VF1000
廠商: Freescale Semiconductor
文件頁數(shù): 43/56頁
文件大?。?/td> 0K
描述: DSP 16BIT W/DDR CTRLR 400-MAPBGA
標準包裝: 90
系列: StarCore
類型: SC1400 內(nèi)核
接口: 主機接口,I²C,UART
時鐘速率: 266MHz
非易失內(nèi)存: 外部
芯片上RAM: 400kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 400-LFBGA
供應商設備封裝: 400-MAPBGA(17x17)
包裝: 托盤
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Hardware Design Considerations
Freescale Semiconductor
48
3.3.4
External I/O Power
The estimation of the I/O power is similar to the computation of the peripheral power estimates. The power consumption per
signal line is computed assuming a maximum load of 20 pF, a voltage swing of 3.3 V, and a switching frequency of 25 MHz or
33 MHz, which yields:
PIO = 20 pF × (3.3 V)
2 × 25 MHz × 10–3 = 5.44 mW per I/O line
Eqn. 16
PIO = 20 pF × (3.3 V)
2
× 33 MHz × 10–3 = 7.19 mW per I/O line
Eqn. 17
Multiply this number by the number of I/O signal lines used in the application design to compute the total I/O power.
Note:
The signal loading depends on the board routing. For systems using a single DDR device, the load could be as low as
7 pF.
3.3.5
Leakage Power
The leakage power is for all power supplies combined at a specific temperature. The value is temperature dependent. The
observed leakage value at room temperature is 64 mW.
3.3.6
Example Total Power Consumption
Using the examples in this section and assuming four peripherals and 10 I/O lines active, a total power consumption value is
estimated as the following:
PTOTAL (200 MHz core) = 216 + (4 × 2.88) + 324,2 + (10 × 5.44) + 64 = 670.12 mW
Eqn. 18
PTOTAL (266 MHz core) = 287 + (4 × 3.83) + 326.3 + (10 × 7.19) + 64 = 764.52 mW
Eqn. 19
3.4
Reset and Boot
This section describes the recommendations for configuring the MSC7115 at reset and boot.
3.4.1
Reset Circuit
HRESET
is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain device. For
an open-drain output such as HRESET, take care when driving many buffers that implement input bus-hold circuitry. The
bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic level to low. Either a smaller
value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7115 output
current, the pull-up value should not be too small (a 1 K
Ω pull-up resistor is used in the MSC711xADS reference design).
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