參數(shù)資料
型號(hào)： MSC1201Y2RHHRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC36
封裝： GREEN, PLASTIC, QFN-36
文件頁數(shù)： 79/93頁
文件大?。?/td> 1093K
代理商： MSC1201Y2RHHRG4
MSC1200
MSC1201
MSC1202
SBAS317E APRIL 2004 REVISED MAY 2006
www.ti.com
80
Phase Lock Loop High (PLLH)
7
6
5
4
3
2
1
0
Reset Value
SFR F5h
CLKSTAT2
CLKSTAT1
CLKSTAT0
PLLLOCK
0
PLL9
PLL8
xxh
CLKSTAT20
Active Clock Status (read-only). Derived from HCR2 setting; refer to Table 3.
bits 75
000: Reserved
001: Reserved
010: Reserved
011: External Clock Mode
100: PLL High-Frequency (HF) Mode (must read PLLLOCK to determine active clock status)
101: PLL Low-Frequency (LF) Mode (must read PLLLOCK to determine active clock status)
110: Internal Oscillator High-Frequency (HF) Mode
111: Internal Oscillator Low-Frequency (LF) Mode
PLLLOCK
PLL Lock Status and Status Enable.
bit 4
For Write (PLL Lock Status Enable):
0 = No Effect
1 = Enable PLL Lock Detection (must wait 20ms before PLLLOCK read status is valid).
For Read (PLL Lock Status):
0 = PLL Not Locked (PLL may be inactive; refer to Table 3 for active clock mode)
1 = PLL Locked (PLL is active clock).
PLL98
PLL Counter Value Most Significant 2 Bits (refer to PLLL, SFR F4h).
bits 10
Analog Clock (ACLK)
7
6
5
4
3
2
1
0
Reset Value
SFR F6h
0
FREQ6
FREQ5
FREQ4
FREQ3
FREQ2
FREQ1
FREQ0
03h
FREQ60
Clock Frequency 1. This value + 1 divides the system clock to create the ADC clock.
bits 60
f
ACLK +
f
CLK
ACLK
) 1
, where f
CLK +
f
OSC
SYSCLK divider
.
f
MOD +
f
ACLK
64
ADC Data Rate
+ f
DATA +
f
MOD
Decimation Ratio
System Reset (SRST)
7
6
5
4
3
2
1
0
Reset Value
SFR F7h
0
RSTREQ
00h
RSTREQ
Reset Request. Setting this bit to ‘1’ and then clearing to ‘0’ will generate a system reset.
bit 0
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