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參數(shù)資料
| 型號： | MS80C51T-16D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44 |
| 文件頁數(shù)： | 22/80頁 |
| 文件大小： | 5152K |
| 代理商： | MS80C51T-16D |
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213
2466T–AVR–07/10
ATmega16(L)
Figure 106. ADC Power Connections
Offset Compensation
Schemes
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea-
surements as much as possible. The remaining offset in the analog path can be measured
directly by selecting the same channel for both differential inputs. This offset residue can be then
subtracted in software from the measurement results. Using this kind of software based offset
correction, offset on any channel can be reduced below one LSB.
ADC Accuracy
Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and V
REF in 2
n steps
(LSBs). The lowest code is read as 0, and the highest code is read as 2
n-1.
Several parameters describe the deviation from the ideal behavior:
Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
(at 0.5 LSB). Ideal value: 0 LSB.
GND
VCC
P
A0
(ADC0)
P
A1
(ADC1)
P
A2
(ADC2)
PA
3
(ADC
3
)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
AVCC
GND
PC7
10
H
100
nF
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