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參數(shù)資料
| 型號(hào)： | MS80C51-12D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 33/80頁 |
| 文件大小： | 5152K |
| 代理商： | MS80C51-12D |
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224
2466T–AVR–07/10
ATmega16(L)
Figure 113. TAP Controller State Diagram
TAP Controller
The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-
scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions
depicted in Figure 113 depend on the signal present on TMS (shown adjacent to each state tran-
sition) at the time of the rising edge at TCK. The initial state after a Power-On Reset is Test-
Logic-Reset.
As a definition in this document, the LSB is shifted in and out first for all Shift Registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:
At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift
Instruction Register – Shift-IR state. While in this state, shift the four bits of the JTAG
instructions into the JTAG Instruction Register from the TDI input at the rising edge of TCK.
The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR
state. The MSB of the instruction is shifted in when this state is left by setting TMS high.
While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out
Test-Logic-Reset
Run-Test/Idle
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Select-DR Scan
Capture-DR
0
1
0
11
1
00
11
1
0
1
0
1
0
1
0
1
0
1
0
1
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