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參數(shù)資料
| 型號(hào)： | MS622424 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 8K x 24 BIT CMOS COLOR MAP |
| 中文描述： | 高性能8K的× 24位CMOS彩色地圖 |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 70K |
| 代理商： | MS622424 |
8-1
MS622424
MOSEL V ITELIC
MS622424 Rev. 1.0 January 1995
MS622424
HIGH PERFORMANCE
8K x 24 BIT
CMOS COLOR MAP
Features
I
Color Index Mode supports up to 8192 simulta-
neous colors out of 16.7 million total colors
I
24-bit RGB Mode allows full true color display
I
High-speed operation capable of supporting
resolutions up 1280 x 1024
I
Available in 100-pin PQFP and MQUAD
packages
I
Unique “Write-Buffer” at MPU port permits
dualport-like operation using an economical
singleport memory core
I
All TTL compatible inputs and outputs
I
60, 70 and 80 MHz pipelined operation
I
Standard MPU Interface
Description
The MS622424 is a high performance, full
CMOS, 8K x 24, 192K-bit pipelined static memory.
This device is specifically designed for use as a
color look-up table in high resolution video display
systems. When two of these devices are operated
in parallel, the resulting system will be capable of
supporting a display of 1280 x 1024 bit mapped
color graphics with 13 bits per pixel in the Color
Index Mode or 24 bits per pixel in the RGB Mode.
In the Color Index Mode, three internal 8Kx8’s
provide 8192 simultaneous colors from a 16.7
million color palette. The palette can be partitioned
into several smaller palettes thereby supporting
multiple window display. In the RGB Mode, the 24-
bit input can be gamma corrected on one of three
gamma correction tables. The 24-bit gamma
corrected value will then be presented at the output.
This device is implemented in full CMOS for low
power consumption, and is available in an 100-pin
plastic or metal quad-flat-pack.
Functional Block Diagram
INPUT
LATCH
PIXIN(0-23)
PIX.RGB(0-1)
CEB1
CEB2
R/WB
CONFIGSEL(0-2)
CONFIGBUS(0-7)
CBLANKB
RSB
BD.REV(0-3)
MPU
CONTROL
2:1 MUX
2:1 MUX
2:1 MUX
PIXIN(0-12)
PIXIN(0-7)
PIXIN(0-12)
PIXIN(8-15)
PIXIN(0-12)
PIXIN(16-23)
PIX.RGB(MUX CONTROL)
3:1 MUX
3:1 MUX
3:1 MUX
13
13
13
ADDR 13
64X37
WRITE
FIFO
RGB 24
FIFO ADDR 13
FIFO RGB 24
8Kx8
8Kx8
8Kx8
13
13
13
8
8
8
OUTPUT
LATCH
POUT(0-23)
24
AFB
FFB
PIPE.OUT(0-3)
PIPELINE SYNCHRONIZATION PATH
CLOCK.IN
PIPE.IN(0-3)
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