
35
8246B–AVR–09/11
ATtiny2313A/4313
mode.
7.1.2
Power-Down Mode
When the SM1:0 bits are written to 01/11, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watch-
dog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out
Reset, an external level interrupt on INT0 and INT1, or a pin change interrupt can wake up the
MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules
only.
7.1.3
Standby Mode
When the SM1..0 bits are 10 and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in six clock cycles.
7.2
Software BOD Disable
179), the BOD is actively monitoring the supply voltage during a sleep period. In some devices it
is possible to save power by disabling the BOD by software in Power-Down and Stand-By sleep
modes. The sleep mode power consumption will then be at the same level as when BOD is glob-
ally disabled by fuses.
If BOD is disabled by software, the BOD function is turned off immediately after entering the
sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe
operation in case the V
CC level has dropped during the sleep period.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately
60s to ensure that the BOD is working correctly before the MCU continues executing code.
BOD disable is controlled by the BODS (BOD Sleep) bit of BOD Control Register, see
“BODCRPower-Down and Stand-By, while writing a zero keeps the BOD active. The default setting is
zero, i.e. BOD active.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see
“BODCR –7.3
Power Reduction Register
vides a method to reduce power consumption by stopping the clock to individual peripherals.
When the clock for a peripheral is stopped then:
The current state of the peripheral is frozen.
The associated registers can not be read or written.
Resources used by the peripheral will remain occupied.
The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit
wakes up the peripheral and puts it in the same state as before shutdown.