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| 型號： | MR80C52TXXX-36SHXXX |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 13/60頁 |
| 文件大小： | 5137K |
| 代理商： | MR80C52TXXX-36SHXXX |
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20
8266D-MCU Wireless-06/12
ATmega128RFA1
Figure 8-8. On-Chip Data SRAM Access Cycles
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute Address
Read
Wr
ite
CPU
Memory Access Instruction
Next Instruction
8.3 EEPROM Data Memory
The ATmega128RFA1 contains 4K Bytes of data EEPROM memory. It is organized as
a separate data space. Read access is byte-wise. The access between the EEPROM
and the CPU is described in the following, specifying the EEPROM Address Registers,
the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,
486, and "Programming the EEPROM" on page 497 respectively.
8.3.1 EEPROM Read Write Access
The EEPROM Access Registers are accessible in the I/O space, see "EEPROM
The write access time for the EEPROM is given in Table 8-3 below. A self-timing
function, however, lets the user software detect when the next byte can be written. If the
user code contains instructions that write the EEPROM, some precautions must be
taken. In heavily filtered power supplies, DVDD is likely to rise or fall slowly on power-
up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. See "Preventing EEPROM
Corruption" on page 24 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be
followed. See the description of the EEPROM Control Register for details on this,
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
The calibrated oscillator is used to time the EEPROM accesses. The following table
lists the typical programming time for EEPROM access from the CPU.
Table 8-3. EEPROM Programming Time
Symbol
Typical Programming time
EEPROM write (from CPU)
4.5 ms
EEPROM erase (from CPU)
8.5 ms
相關PDF資料 |
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| IQ80C52XXX-16SHXXX:RD | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| IF180C52TXXX-36:RD | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| IT80C52EXXX-30SHXXX:R | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP44 |
| MC80C52CXXX-20/883D | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
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