參數(shù)資料
型號: MR80C52EXXX-12/883:R
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44
封裝: LCC-44
文件頁數(shù): 58/141頁
文件大?。?/td> 7628K
235
8021G–AVR–03/11
ATmega329P/3290P
Figure 23-6. Driving a LCD with Four Common Terminals
23.3.5
Low Power Waveform
To reduce toggle activity and hence power consumption a low power waveform can be selected
by writing LCDAB to one. Low power waveform requires two subsequent frames with the same
display data to obtain zero DC voltage. Consequently data latching and Interrupt Flag is only set
every second frame. Default and low power waveform is shown in Figure 23-7 for 1/3 duty and
1/3 bias. For other selections of duty and bias, the effect is similar.
Figure 23-7. Default and Low Power Waveform
23.3.6
Operation in Sleep Mode
When synchronous LCD clock is selected (LCDCS = 0) the LCD display will operate in Idle
mode and Power-save mode with any clock source.
An asynchronous clock from TOSC1 can be selected as LCD clock by writing the LCDCS bit to
one when Calibrated Internal RC Oscillator is selected as system clock source. The LCD will
then operate in Idle mode, ADC Noise Reduction mode and Power-save mode.
When EXCLK in ASSR Register is written to one, and asynchronous clock is selected, the exter-
nal clock input buffer is enabled and an external clock can be input on Timer Oscillator 1
VLCD
2/
3VLCD
1/
3VLCD
GND
VLCD
2/
3VLCD
1/
3VLCD
GND
VLCD
2/
3VLCD
1/
3VLCD
GND
-1/3VLCD
-2/3VLCD
-VLCD
SEG0
COM0
SEG0 - COM0
Frame
VLCD
2/
3VLCD
1/
3VLCD
GND
VLCD
2/
3VLCD
1/
3VLCD
GND
VLCD
2/
3VLCD
1/
3VLCD
GND
-1/3VLCD
-2/3VLCD
-VLCD
SEG0
COM1
SEG0 - COM1
Frame
VLCD
2/
3VLCD
1/
3VLCD
GND
VLCD
2/
3VLCD
1/
3VLCD
GND
VLCD
2/
3VLCD
1/
3VLCD
GND
-1/3VLCD
-2/3VLCD
-VLCD
SEG0
COM0
SEG0 - COM0
Frame
VLCD
2/
3VLCD
1/
3VLCD
GND
VLCD
2/
3VLCD
1/
3VLCD
GND
VLCD
2/
3VLCD
1/
3VLCD
GND
-1/3VLCD
-2/3VLCD
-VLCD
SEG0
COM0
SEG0 - COM0
Frame
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