參數(shù)資料
型號： MR80C52CXXX-20
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù)： 162/170頁
文件大?。?/td> 25028K
代理商： MR80C52CXXX-20
244
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
23. ADC - Analog-to-digital converter
23.1
Features
10-bit resolution
0.5LSB integral non-linearity
±2LSB absolute accuracy
13 - 260s conversion time
Up to 15kSPS at maximum resolution
Eight multiplexed single ended input channels
Differential mode with selectable gain at 1×, 10×, or 200×
Optional left adjustment for ADC result readout
0 - V
CC ADC input voltage range
2.7 - V
CC differential ADC voltage range
Selectable 2.56V or 1.1V ADC reference voltage
Free Running or Single Conversion mode
ADC start conversion by auto triggering on interrupt sources
Interrupt on ADC conversion complete
Sleep mode noise canceler
Note:
1. The differential input channels are not tested for devices in PDIP package. This feature is only
guaranteed to work for devices in TQFP, VQFN/QFN/MLF, VFBGA and DRQFN packages.
23.2
Overview
The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features a 10-bit suc-
cessive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer which
allows 8 single-ended voltage inputs constructed from the pins of Port A. The single-ended volt-
age inputs refer to 0V (GND).
The device also supports 16 differential voltage input combinations. Two of the differential inputs
(ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage. This provides
amplification steps of 0 dB (1×), 20 dB (10×), or 46 dB (200×) on the differential input voltage
before the A/D conversion. Seven differential analog input channels share a common negative
terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1×
or 10× gain is used, 8-bit resolution can be expected. If 200× gain is used, 6-bit resolution can
be expected. Note that internal references of 1.1V should not be used on 10× and 200× gain.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 23-1
The ADC has a separate analog supply voltage pin, AV
CC. AVCC must not differ more than ±0.3V
from V
CC. See the paragraph ”ADC Noise Canceler” on page 252 on how to connect this pin.
Internal reference voltages of nominally 1.1V, 2.56V, or AV
CC are provided On-chip. The voltage
reference may be externally decoupled at the AREF pin by a capacitor for better noise perfor-
mance. If V
CC is below 2.1V, internal voltage reference of 1.1V should not be used on single
ended channels.
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