參數資料
型號: MR80C32-36:RD
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 36 MHz, MICROCONTROLLER, CQCC44
封裝: LCC-44
文件頁數: 108/120頁
文件大小: 25028K
196
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 19-5.
UPMn bits settings.
UPMn1
UPMn0
Parity Mode
0
Disabled
01
Reserved
1
0
Enabled, Even Parity
1
Enabled, Odd Parity
Table 19-6.
USBS bit settings.
USBSn
Stop bit(s)
01-bit
12-bit
Table 19-7.
UCSZn bits settings.
UCSZn2
UCSZn1
UCSZn0
Character Size
000
5-bit
001
6-bit
010
7-bit
011
8-bit
100
Reserved
101
Reserved
110
Reserved
111
9-bit
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