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參數(shù)資料
| 型號(hào)： | MR80C32-12P883D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 10/91頁 |
| 文件大?。?/td> | 19688K |
| 代理商： | MR80C32-12P883D |
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149
7679H–CAN–08/08
AT90CAN32/64/128
Register to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2A Register access may seem complex, but this is not case. When the double buffer-
ing is enabled, the CPU has access to the OCR2A Buffer Register, and if double buffering is
disabled the CPU will access the OCR2A directly.
14.5.1
Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC2A) bit. Forcing compare match will not set the
OCF2A flag or reload/clear the timer, but the OC2A pin will be updated as if a real compare
match had occurred (the COM2A1:0 bits settings define whether the OC2A pin is set, cleared or
toggled).
14.5.2
Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2A to be initial-
ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is
enabled.
14.5.3
Using the Output Compare Unit
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT2 when using the Output Compare channel,
independently of whether the Timer/Counter is running or not. If the value written to TCNT2
equals the OCR2A value, the compare match will be missed, resulting in incorrect waveform
generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is
downcounting.
The setup of the OC2A should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC2A value is to use the Force Output Com-
pare (FOC2A) strobe bit in Normal mode. The OC2A Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COM2A1:0 bits are not double buffered together with the compare value.
Changing the COM2A1:0 bits will take effect immediately.
14.6
Compare Match Output Unit
The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Generator
uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next compare
match. Also, the COM2A1:0 bits control the OC2A pin output source. Figure 14-5 shows a sim-
plified schematic of the logic affected by the COM2A1:0 bit setting. The I/O Registers, I/O bits,
and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control regis-
ters (DDR and PORT) that are affected by the COM2A1:0 bits are shown. When referring to the
OC2A state, the reference is for the internal OC2A Register, not the OC2A pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MR80C32-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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| MR80C32-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MR80C32-36 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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