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參數(shù)資料
| 型號(hào)： | MQFL-270-12D-Z-ES |
| 廠商： | SYNQOR INC |
| 元件分類(lèi)： | 電源模塊 |
| 英文描述： | 2-OUTPUT 120 W DC-DC REG PWR SUPPLY MODULE |
| 封裝： | MODULE-12 |
| 文件頁(yè)數(shù)： | 3/19頁(yè) |
| 文件大?。?/td> | 3903K |
| 代理商： | MQFL-270-12D-Z-ES |
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Product # MQFL-270-12D
Phone 1-888-567-9596
www.synqor.com
Doc.# 005-0005043 Rev. B
02/07/11
Page 11
Output:
Current:
±12V
10A
MQFL-270-12D
Application Section
BASIC OPERATION AND FEATURES
The MQFL dc-dc converter uses a two-stage power conversion
topology. The first, or regulation, stage is a buck-converter
that keeps the output voltage constant over variations in line,
load, and temperature. The second, or isolation, stage uses
transformers to provide the functions of input/output isolation
and voltage transformation to achieve the output voltage
required.
In the dual output converter there are two secondary windings
in the transformer of the isolation stage, one for each output.
There is only one regulation stage, however, and it is used
to control the positive output. The negative output therefore
displays “Cross-Regulation”, meaning that its output voltage
depends on how much current is drawn from each output.
Both the positive and the negative outputs share a common
OUTPUT RETURN pin.
Both the regulation and the isolation stages switch at a fixed
frequency for predictable EMI performance. The isolation
stage switches at one half the frequency of the regulation
stage, but due to the push-pull nature of this stage it creates
a ripple at double its switching frequency. As a result, both
the input and the output of the converter have a fundamental
ripple frequency of about 550 kHz in the free-running mode.
Rectification of the isolation stage’s output is accomplished with
synchronous rectifiers. These devices, which are MOSFETs
with a very low resistance, dissipate far less energy than would
Schottky diodes. This is the primary reason why the MQFL
converters have such high efficiency, particularly at low output
voltages.
Besides improving efficiency, the synchronous rectifiers permit
operation down to zero load current. There is no longer a need
for a minimum load, as is typical for converters that use diodes
for rectification. The synchronous rectifiers actually permit a
negative load current to flow back into the converter’s output
terminals if the load is a source of short or long term energy.
The MQFL converters employ a “back-drive current limit” to
keep this negative output terminal current small.
There is a control circuit on both the input and output sides of
the MQFL converter that determines the conduction state of the
power switches. These circuits communicate with each other
across the isolation barrier through a magnetically coupled
device. No opto-isolators are used. A separate bias supply
provides power to both the input and output control circuits.
An input under-voltage lockout feature with hysteresis is
provided, as well as an input over-voltage shutdown. There
is also an output current limit that is nearly constant as the
load impedance decreases to a short circuit (i.e., there is no
fold-back or fold-forward characteristic to the output current
under this condition). When a load fault is removed, the
output voltage rises exponentially to its nominal value without
an overshoot.
The MQFL converter’s control circuit does not implement an
output over-voltage limit or an over-temperature shutdown.
The following sections describe the use and operation of
additional control features provided by the MQFL converter.
CONTROL FEATURES
ENABLE: The MQFL converter has two enable pins. Both
must have a logic high level for the converter to be enabled. A
logic low on either pin will inhibit the converter.
The ENA1 pin (pin 4) is referenced with respect to the
converter’s input return (pin 2). The ENA2 pin (pin 12) is
referenced with respect to the converter’s output return (pin
8). This permits the converter to be inhibited from either the
input or the output side.
Regardless of which pin is used to inhibit the converter, the
regulation and the isolation stages are turned off. However,
when the converter is inhibited through the ENA1 pin, the bias
supply is also turned off, whereas this supply remains on when
the converter is inhibited through the ENA2 pin. A higher input
standby current therefore results in the latter case.
Both enable pins are internally pulled high so that an open
connection on both pins will enable the converter. Figure A
shows the equivalent circuit looking into either enable pins. It
is TTL compatible.
2N3904
1N4148
250K
125K
68K
5.0V
TO ENABLE
CIRCUITRY
PIN 4
(OR PIN 12)
PIN 2
(OR PIN 8)
IN RTN
ENABLE
Figure A: Circuit diagram shown for reference only, actual circuit
components may differ from values shown for equivalent circuit.
COL 1
COL 2
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