
298
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
28.7
External interrupts characteristics
28.8
SPI timing characteristics
Note:
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t
CLCL for fCK < 12MHz.
- 3 t
CLCL for fCK > 12MHz.
Table 28-15. Asynchronous external interrupt characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
tINT
Minimum pulse width for asynchronous external interrupt
50
ns
Table 28-16. SPI timing parameters.
Description
Mode
Minimum
Typical
Maximum
Units
1
SCK period
Master
ns
2
SCK high/low
Master
50% duty cycle
3
Rise/Fall time
Master
3.6
4
Setup
Master
10
5
Hold
Master
10
6
Out to SCK
Master
0.5 tsck
7
SCK to out
Master
10
8
SCK to out high
Master
10
9SS low to out
Slave
15
10
SCK period
Slave
4 tck
11
Slave
2 tck
12
Rise/Fall time
Slave
1.6
s
13
Setup
Slave
10
ns
14
Hold
Slave
tck
15
SCK to out
Slave
15
16
SCK to SS high
Slave
20
17
SS high to tri-state
Slave
10
18
SS low to SCK
Slave
20 tck