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參數(shù)資料
| 型號(hào)： | MQ83C154TXXX-12/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁(yè)數(shù)： | 141/326頁(yè) |
| 文件大?。?/td> | 61013K |
| 代理商： | MQ83C154TXXX-12/883 |
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225
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Note:
1. Incorrect setting of the switches in Figure 25-9 on page 223 will make signal contention and may damage the part.
There are several input choices to the S&H circuitry on the negative input of the output comparator in Figure 25-9
on page 223. Make sure only one path is selected from either one ADC pin, Bandgap reference source, or Ground.
If the ADC is not to be used during scan, the recommended input values from Table 25-3 on page 223 should be
used. The user is recommended not to use the Differential Amplifier during scan. Switch-Cap based differential
amplifier requires fast operation and accurate timing which is difficult to obtain when used in a scan chain. Details
concerning operations of the differential amplifier is therefore not provided.
The AVR ADC is based on the analog circuitry shown in Figure 25-9 on page 223 with a successive approximation
algorithm implemented in the digital logic. When used in Boundary-scan, the problem is usually to ensure that an
applied analog voltage is measured within some limits. This can easily be done without running a successive
approximation algorithm: apply the lower limit on the digital DAC[9:0] lines, make sure the output from the compar-
ator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify the output from the comparator to be
high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as
well.
When using the ADC, remember the following
The port pin for the ADC channel in use must be configured to be an input with pull-up disabled to avoid signal
contention
In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when enabling the ADC. The
user is advised to wait at least 200ns after enabling the ADC before controlling/observing any ADC signal, or
perform a dummy conversion before using the first result
The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample mode)
As an example, consider the task of verifying a 1.5V ±5% input signal at ADC channel 3 when the power supply is
5.0V and AREF is externally connected to V
CC.
The recommended values from Table 25-3 on page 223 are used unless other values are given in the algorithm in
Table 25-4 on page 226. Only the DAC and port pin values of the Scan Chain are shown. The column “Actions”
describes what JTAG instruction to be used before filling the Boundary-scan Register with the succeeding col-
umns. The verification should be done on the data scanned out when scanning in the data on the same row in the
table.
SCTEST
Input
Switch-cap TEST enable. Output
from differential amplifier is sent out
to Port Pin having ADC_4
00
ST
Input
Output of differential amplifier will
settle faster if this signal is high first
two ACLK periods after AMPEN
goes high.
00
VCCREN
Input
Selects Vcc as the ACC reference
voltage.
00
Table 25-3.
Boundary-scan Signals for the ADC
(1). (Continued)
Signal name
Direction as seen
from the ADC
Description
Recommended
Input when not
in use
Output values when
recommended inputs are used,
and CPU is not using the ADC
The lower limit is:
1024 1.5V 0,95 5V
291
0x123
==
The upper limit is:
1024 1.5V 1.05 5V
323
0x143
==
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