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| 型號(hào)： | MQ80C52XXX-36SHXXX |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁(yè)數(shù)： | 63/132頁(yè) |
| 文件大?。?/td> | 10886K |
| 代理商： | MQ80C52XXX-36SHXXX |
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268
8151H–AVR–02/11
ATmega128A
Note:
Incorrect setting of the switches in Figure 24-13 will make signal contention and may damage the
part. There are several input choices to the S&H circuitry on the negative input of the output com-
parator in Figure 24-13. Make sure only one path is selected from either one ADC pin, Bandgap
reference source, or Ground.
If the ADC is not to be used during scan, the recommended input values from Table 24-5 should
be used. The user is recommended not to use the Differential Gain stages during scan. Switch-
Cap based gain stages require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential gain stage is there-
fore not provided.
The AVR ADC is based on the analog circuitry shown in Figure 24-13 with a successive approx-
imation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is
usually to ensure that an applied analog voltage is measured within some limits. This can easily
be done without running a successive approximation algorithm: apply the lower limit on the digi-
tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit
on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following
The Port Pin for the ADC channel in use must be configured to be an input with pull-up
disabled to avoid signal contention.
In normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal
low (Sample mode).
As an example, consider the task of verifying a 1.5V ±5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
CC.
The recommended values from Table 24-5 are used unless other values are given in the algo-
rithm in Table 24-6. Only the DAC and Port Pin values of the Scan Chain are shown. The
column “Actions” describes what JTAG instruction to be used before filling the Boundary-scan
Register with the succeeding columns. The verification should be done on the data scanned out
when scanning in the data on the same row in the table.
Table 24-6.
Algorithm for Using the ADC
Step
Actions
ADCEN
DAC
MUXEN
HOLD
PRECH
PA3.
Data
PA3.
Control
PA3.
Pullup_
Enable
1
SAMPLE_P
RELOAD
1
0x200
0x08
1
0
2
EXTEST
1
0x200
0x08
0
1
0
3
1
0x200
0x08
1
0
4
1
0x123
0x08
1
0
5
1
0x123
0x08
1
0
The lower limit is:
1024 1.5
V 0,95 5V
291
0x123
==
The upper limit is:
1024 1.5
V 1.05 5V
323
0x143
==
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