
140
7734Q–AVR–02/12
AT90PWM81/161
12.25.9
PCTL2 - PSC 2 Control Register
Bit 7:6 – PPREn1:0 : PSC n Prescaler Select
This two bits select the PSC input clock division factor. All generated waveform will be modified
by this factor.
Bit 5 – PBFMn0: Balance Flank Width Modulation bit 0
Defines the Flank Width Modulation, together with PBFMn1 bit in PCNFEn register. See
Table Bit 4 – PAOCnB: PSC n Asynchronous Output Control B
When this bit is set, Fault input selected to block B can act directly to PSCOUTn1 and
Bit 3 – PAOCnA: PSC n Asynchronous Output Control A
When this bit is set, Fault input selected to block A can act directly to PSCOUTn0 and
Bit 2 – PARUNn: PSC n Autorun
When this bit is set, the PSC n starts with PSCn-1. That means that PSC n starts:
when PRUNn bit in PCTLn register is set,
or when PARUNn bit in PCTLn is set and PRUNn-1 bit in PCTLn-1 register is set (or PARUN0
bit and PRUN0)
Bit 1 – PCCYCn: PSC n Complete Cycle
When this bit is set, the PSC n completes the entire waveform cycle before halt operation
requested by clearing PRUNn. This bit is not relevant in slave mode (PARUNn = 1).
Bit 0 – PRUNn: PSC n Run
Writing this bit to one starts the PSC n.
When set, this bit prevails over PARUNn bit.
Bit
7
6
5
4
3210
PPRE21
PPRE20
PBFM20
PAOC2B
PAOC2A
PARUN2
PCCYC2
PRUN2
PCTL2
Read/Write
R/W
Initial Value
0
0000
Table 12-20. PSC n Prescaler selection.
PPREn1
PPREn0
Description
0
No divider on PSC input clock
0
1
Divide the PSC input clock by 4
1
0
Divide the PSC input clock by 16
1
Divide the PSC clock by 64