參數(shù)資料
型號: MQ80C52XXX-36/883
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
封裝: CERAMIC, QFP-44
文件頁數(shù): 59/152頁
文件大小: 2528K
代理商: MQ80C52XXX-36/883
151
2486AA–AVR–02/2013
ATmega8(L)
Bit 5:4 – UPM1:0: Parity Mode
These bits enable and set type of Parity Generation and Check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting.
If a mismatch is detected, the PE Flag in UCSRA will be set.
Bit 3 – USBS: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Bit 2:1 – UCSZ1:0: Character Size
The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Char-
acter Size) in a frame the Receiver and Transmitter use.
Table 56. UPM Bits Settings
UPM1
UPM0
Parity Mode
0
Disabled
01
Reserved
1
0
Enabled, Even Parity
1
Enabled, Odd Parity
Table 57. USBS Bit Settings
USBS
Stop Bit(s)
01-bit
12-bit
Table 58. UCSZ Bits Settings
UCSZ2
UCSZ1
UCSZ0
Character Size
000
5-bit
001
6-bit
010
7-bit
011
8-bit
100
Reserved
101
Reserved
110
Reserved
111
9-bit
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