
706
11028E–ATARM–22-Apr-13
SAM9G46
Figure 36-5. SD Memory Card Bus Topology
The SD Memory Card bus includes the signals listed in
Table 36-3.
Notes:
1. I: input, O: output, PP: Push Pull, OD: Open Drain.
2. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK,
MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy.
Figure 36-6. SD Card Bus Connections with One Slot
Note:
When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy
to HSMCIx_DAy.
When the HSMCI is configured to operate with SD memory cards, the width of the data bus can
be selected in the HSMCI_SDCR register. Clearing the SDCBUS bit in this register means that
the width is one bit; setting it means that the width is four bits. In the case of High Speed Multi-
Media cards, only the data line 0 is used. The other data lines can be used as independent
PIOs.
36.8
High Speed MultiMedia Card Operations
After a power-on reset, the cards are initialized by a special message-based High Speed Multi-
Media Card bus protocol. Each message is represented by one of the following tokens:
2345 6
17 8
SD CARD
9
Table 36-3.
SD Memory Card Bus Signals
Pin
Number
Name
Type(1)
Description
HSMCI Pin
Name(2)
(Slot z)
1
CD/DAT[3]
I/O/PP
Card detect/ Data line Bit 3
MCDz3
2
CMD
PP
Command/response
MCCDz
3
VSS1
S
Supply voltage ground
VSS
4
VDD
S
Supply voltage
VDD
5
CLK
I/O
Clock
MCCK
6
VSS2
S
Supply voltage ground
VSS
7
DAT[0]
I/O/PP
Data line Bit 0
MCDz0
8
DAT[1]
I/O/PP
Data line Bit 1 or Interrupt
MCDz1
9
DAT[2]
I/O/PP
Data line Bit 2
MCDz2
2345
6
17
MCDA0 - MCDA3
MCCDA
MCCK
8
SD CARD
9