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  • 參數(shù)資料
    型號: MQ80C52TXXX-16SHXXX:RD
    廠商: TEMIC SEMICONDUCTORS
    元件分類: 微控制器/微處理器
    英文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44
    文件頁數(shù): 18/83頁
    文件大?。?/td> 8336K
    19
    8021G–AVR–03/11
    ATmega329P/3290P
    The Atmel
    AVR ATmega329P/3290P is a complex microcontroller with more peripheral units
    than can be supported within the 64 locations reserved in the Opcode for the IN and OUT
    instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
    LD/LDS/LDD instructions can be used.
    The lower 2304 data memory locations address both the Register File, the I/O memory,
    Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register
    File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory,
    and the next 2048/locations address the internal data SRAM.
    The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
    ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
    File, registers R26 to R31 feature the indirect addressing pointer registers.
    The direct addressing reaches the entire data space.
    The Indirect with Displacement mode reaches 63 address locations from the base address given
    by the Y- or Z-register.
    When using register indirect addressing modes with automatic pre-decrement and post-incre-
    ment, the address registers X, Y, and Z are decremented or incremented.
    The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
    the 2,048bytes of internal data SRAM in the ATmega329P/3290P are all accessible through all
    these addressing modes. The Register File is described in ”General Purpose Register File” on
    Figure 7-2.
    Data Memory Map
    7.3.1
    Data Memory Access Times
    This section describes the general access timing concepts for internal memory access. The
    internal data SRAM access is performed in two clk
    CPU cycles as described in Figure 7-3.
    32 Registers
    64 I/O Registers
    Internal SRAM
    (2048 x 8)
    0x0000 - 0x001F
    0x0020 - 0x005F
    0x08FF
    0x0060 - 0x00FF
    Data Memory
    160 Ext I/O Reg.
    0x0100
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