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參數(shù)資料
| 型號： | MQ80C52TXXX-12SB |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 20/46頁 |
| 文件大?。?/td> | 4720K |
| 代理商： | MQ80C52TXXX-12SB |
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26
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
7.5
Register Description
7.5.1
MCUCR – MCU Control Register
The MCU Control Register contains bits for controlling external interrupt sensing and power management.
Bit 5 – Res: Reserved Bit
This bit is reserved and will always read as zero.
Bit 4 – BODS: BOD Sleep
In order to disable BOD during sleep (see Table 7-1 on page 23) the BODS bit must be written to logic one. This is
controlled by a protected change sequence, as follows:
1.
Write the signature for change enable of protected I/O registers to register CCP.
2.
Within four instruction cycles write the BODS bit.
A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode.
The BODS bit is automatically cleared when the device wakes up. Alternatively the BODS bit can be cleared by writing
logic zero to it. This does not require protected sequence.
Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2 - 0
These bits select between available sleep modes, as shown in Table 7-2.
Table 7-2.
Sleep Mode Select
Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.
To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep
Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.
Bit
765432
1
0
ISC01
ISC00
–
BODS
SM2
SM1
SM0
SE
MCUCR
Read/Write
R/W
R
R/W
Initial Value
0
SM2
SM1
SM0
Sleep Mode
0
Idle
0
1
ADC noise reduction
0
1
0
Power-down
0
1
Reserved
1
0
Standby
1
0
1
Reserved
1
0
Reserved
1
Reserved
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