參數(shù)資料
型號(hào)： MQ80C52EXXX-30
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQFP44
文件頁數(shù)： 92/134頁
文件大?。?/td> 3805K
代理商： MQ80C52EXXX-30
60
8068U–AVR–06/2013
XMEGA A3
Not recommended for new designs -
Use XMEGA A3U series
Notes:
1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid
for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
ROL
Rd
Rotate Left Through Carry
Rd(0)
Rd(n+1)
C
C,
Rd(n),
Rd(7)
Z,C,N,V,H
1
ROR
Rd
Rotate Right Through Carry
Rd(7)
Rd(n)
C
C,
Rd(n+1),
Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n)
Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)
Rd(7..4)
None
1
BSET
s
Flag Set
SREG(s)
1SREG(s)
1
BCLR
s
Flag Clear
SREG(s)
0SREG(s)
1
SBI
A, b
Set Bit in I/O Register
I/O(A, b)
1
None
1
CBI
A, b
Clear Bit in I/O Register
I/O(A, b)
0
None
1
BST
Rr, b
Bit Store from Register to T
T
Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b)
T
None
1
SEC
Set Carry
C
1C
1
CLC
Clear Carry
C
0C
1
SEN
Set Negative Flag
N
1N
1
CLN
Clear Negative Flag
N
0N
1
SEZ
Set Zero Flag
Z
1Z
1
CLZ
Clear Zero Flag
Z
0Z
1
SEI
Global Interrupt Enable
I
1I
1
CLI
Global Interrupt Disable
I
0I
1
SES
Set Signed Test Flag
S
1S
1
CLS
Clear Signed Test Flag
S
0S
1
SEV
Set Two’s Complement Overflow
V
1V
1
CLV
Clear Two’s Complement Overflow
V
0V
1
SET
Set T in SREG
T
1T
1
CLT
Clear T in SREG
T
0T
1
SEH
Set Half Carry Flag in SREG
H
1H
1
CLH
Clear Half Carry Flag in SREG
H
0H
1
MCU Control Instructions
BREAK
Break
(See specific descr. for BREAK)
None
1
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep)
None
1
WDR
Watchdog Reset
(see specific descr. for WDR)
None
1
Mnemonics
Operands
Description
Operation
Flags
#Clocks
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