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58
2593O–AVR–02/12
ATmega644
0x1F002
ldi
r16,low(RAMEND)
0x1F003
out
SPL,r16
0x1F004
sei
; Enable interrupts
0x1F005
<instr>
xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 8 Kbytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
Address
Labels Code
Comments
;
.org 0x1F000
0x1F000
jmp
RESET
; Reset handler
0x1F002
jmp
EXT_INT0
; IRQ0 Handler
0x1F004
jmp
EXT_INT1
; IRQ1 Handler
...
;
0x1F036
jmp
SPM_RDY
; SPM Ready Handler
;
0x1F03E
RESET: ldi
r16,high(RAMEND); Main program start
0x1F03F
out
SPH,r16
; Set Stack Pointer to top of RAM
0x1F040
ldi
r16,low(RAMEND)
0x1F041
out
SPL,r16
0x1F042
sei
; Enable interrupts
0x1FO43
<instr>
xxx
10.1.1
Moving Interrupts Between Application and Boot Space
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
10.2
Register Description
10.2.1
MCUCR – MCU Control Register
Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-
details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must
be followed to change the IVSEL bit:
a.
Write the Interrupt Vector Change Enable (IVCE) bit to one.
b.
Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
Bit
7
6
543
21
0
JTD
–
PUD
–
IVSEL
IVCE
MCUCR
Read/Write
R/W
R
R/W
R
R/W
Initial Value
0