
Signal Descriptions
A-8
Copyright 2000 ARM Limited. All rights reserved.
ARM DDI 0165B
A.6
Debug signals
Table A-6 Debug signals
Name
Direction
Description
DBGIR[3:0]
TAP controller
instruction register
Output
These four bits reflect the current instruction loaded
into the TAP controller instruction register. These bits
change when the TAP state machine is in the
UPDATE-IR state.
DBGnTRST
Not test reset
Input
This is the active LOW reset signal for the
EmbeddedICE internal state. This signal is a
level-sensitive asynchronous reset input.
DBGnTDOEN
Not DBGTDO
enable
Output
When LOW, this signal denotes that serial data is
being driven out on the DBGTDO output.
DBGnTDOEN is usually used as an output enable
for a DBGTDO pin in a packaged part.
DBGSCREG[4:0]
Output
These five bits reflect the ID number of the scan chain
currently selected by the TAP Scan Chain Register
controller. These bits change when the TAP state
machine is in the UPDATE-DR state.
DBGSDIN
Output boundary
scan serial input
data
Output
This signal contains the serial data to be applied to an
external scan chain.
DBGSDOUT
Input boundary
scan serial output
data
Input
This is the serial data out of an external scan chain.
When an external boundary scan chain is not
connected, this input must be tied LOW.
DBGTAPSM[3:0]
TAP controller state
machine
Output
This bus reflects the current state of the TAP
controller state machine.
DBGTCKEN
Input
Synchronous enable for debug logic accessed using
the JTAG interface.
DBGTDI
Input
Test data input to the debug logic.
DBGTDO
Output
Output from the debug logic.
DBGTMS
Input
Test mode select for the TAP controller.