
240
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
25.8
Boundary-scan Related Register in I/O Memory
25.8.1
MCUCR – MCU Control Register
The MCU Control Register contains control bits for general MCU functions.
Bit 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG
interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence
must be followed when changing this bit: The application software must write this bit to the desired value twice
within four cycles to change its value. Note that this bit must not be altered when using the On-chip Debug system.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to one. The reason for
this is to avoid static current at the TDO pin in the JTAG interface.
25.8.2
MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction
AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
Bit
765
43210
0x35 (0x55)
JTD
-
PUD
–
IVSEL
IVCE
MCUCR
Read/Write
R/W
RR
R/W
RR
R/W
Initial Value
000
00000
Bit
765
43210
0x34 (0x54)
–
–JTRF
WDRF
BORF
EXTRF
PORF
MCUSR
Read/Write
RRR
R/W
Initial Value
0
See Bit Description