
CHAPTER 3 CPU ARCHITECTURE
58
User’s Manual U15075EJ1V0UM00
Figure 3-10. Data Memory Addressing (
μ
PD789445, 789455)
Special function registers (SFRs)
256
×
8 bits
Internal high-speed RAM
512
×
8 bits
Internal ROM
12288
×
8 bits
FFFFH
0000H
Direct addressing
Register indirect
addressing
Based addressing
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
SFR addressing
Short direct
addressing
LCD display RAM
15
×
4 bits
Reserved
Reserved
FD00H
FCFFH
FA00H
F9FFH
3000H
2FFFH
FA0FH
FA0EH